* [PATCH 1/3] drm/amdgpu/gfx11: select HDP ref/mask according to gfx ring pipe
@ 2024-05-02 21:42 Alex Deucher
2024-05-02 21:42 ` [PATCH 2/3] drm/amdgpu/gfx11: handle priority setup for gfx pipe1 Alex Deucher
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Alex Deucher @ 2024-05-02 21:42 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use correct ref/mask for differnent gfx ring pipe. Ported from
ZhenGuo's patch for gfx10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index ad6431013c738..81a35d0f0a58e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -5293,7 +5293,7 @@ static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
}
reg_mem_engine = 0;
} else {
- ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
+ ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
reg_mem_engine = 1; /* pfp */
}
--
2.44.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] drm/amdgpu/gfx11: handle priority setup for gfx pipe1
2024-05-02 21:42 [PATCH 1/3] drm/amdgpu/gfx11: select HDP ref/mask according to gfx ring pipe Alex Deucher
@ 2024-05-02 21:42 ` Alex Deucher
2024-05-02 21:42 ` [PATCH 3/3] drm/amdgpu/gfx11: enable gfx pipe1 hardware support Alex Deucher
2024-05-07 13:26 ` [PATCH 1/3] drm/amdgpu/gfx11: select HDP ref/mask according to gfx ring pipe Alex Deucher
2 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2024-05-02 21:42 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Set up pipe1 as a high priority queue.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 36 ++++++++++++++++++--------
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 81a35d0f0a58e..75157e0196d22 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -929,9 +929,9 @@ static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
int me, int pipe, int queue)
{
- int r;
struct amdgpu_ring *ring;
unsigned int irq_type;
+ unsigned int hw_prio;
ring = &adev->gfx.gfx_ring[ring_id];
@@ -950,11 +950,10 @@ static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
- r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
- AMDGPU_RING_PRIO_DEFAULT, NULL);
- if (r)
- return r;
- return 0;
+ hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
+ AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
+ return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
+ hw_prio, NULL);
}
static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
@@ -3615,6 +3614,24 @@ static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev)
(adev->doorbell_index.userqueue_end * 2) << 2);
}
+static void gfx_v11_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
+ struct v11_gfx_mqd *mqd,
+ struct amdgpu_mqd_prop *prop)
+{
+ bool priority = 0;
+ u32 tmp;
+
+ /* set up default queue priority level
+ * 0x0 = low priority, 0x1 = high priority
+ */
+ if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
+ priority = 1;
+
+ tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY);
+ tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
+ mqd->cp_gfx_hqd_queue_priority = tmp;
+}
+
static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
struct amdgpu_mqd_prop *prop)
{
@@ -3643,11 +3660,8 @@ static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
mqd->cp_gfx_hqd_vmid = 0;
- /* set up default queue priority level
- * 0x0 = low priority, 0x1 = high priority */
- tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY);
- tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
- mqd->cp_gfx_hqd_queue_priority = tmp;
+ /* set up gfx queue priority */
+ gfx_v11_0_gfx_mqd_set_priority(adev, mqd, prop);
/* set up time quantum */
tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM);
--
2.44.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] drm/amdgpu/gfx11: enable gfx pipe1 hardware support
2024-05-02 21:42 [PATCH 1/3] drm/amdgpu/gfx11: select HDP ref/mask according to gfx ring pipe Alex Deucher
2024-05-02 21:42 ` [PATCH 2/3] drm/amdgpu/gfx11: handle priority setup for gfx pipe1 Alex Deucher
@ 2024-05-02 21:42 ` Alex Deucher
2024-05-07 13:26 ` [PATCH 1/3] drm/amdgpu/gfx11: select HDP ref/mask according to gfx ring pipe Alex Deucher
2 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2024-05-02 21:42 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Enable gfx pipe1 hardware support.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 75157e0196d22..de15abc6a0351 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -50,7 +50,7 @@
#include "nbio_v4_3.h"
#include "mes_v11_0.h"
-#define GFX11_NUM_GFX_RINGS 1
+#define GFX11_NUM_GFX_RINGS 2
#define GFX11_MEC_HPD_SIZE 2048
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
@@ -1341,7 +1341,7 @@ static int gfx_v11_0_sw_init(void *handle)
case IP_VERSION(11, 0, 2):
case IP_VERSION(11, 0, 3):
adev->gfx.me.num_me = 1;
- adev->gfx.me.num_pipe_per_me = 1;
+ adev->gfx.me.num_pipe_per_me = 2;
adev->gfx.me.num_queue_per_pipe = 1;
adev->gfx.mec.num_mec = 2;
adev->gfx.mec.num_pipe_per_mec = 4;
@@ -1352,7 +1352,7 @@ static int gfx_v11_0_sw_init(void *handle)
case IP_VERSION(11, 5, 0):
case IP_VERSION(11, 5, 1):
adev->gfx.me.num_me = 1;
- adev->gfx.me.num_pipe_per_me = 1;
+ adev->gfx.me.num_pipe_per_me = 2;
adev->gfx.me.num_queue_per_pipe = 1;
adev->gfx.mec.num_mec = 1;
adev->gfx.mec.num_pipe_per_mec = 4;
--
2.44.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] drm/amdgpu/gfx11: select HDP ref/mask according to gfx ring pipe
2024-05-02 21:42 [PATCH 1/3] drm/amdgpu/gfx11: select HDP ref/mask according to gfx ring pipe Alex Deucher
2024-05-02 21:42 ` [PATCH 2/3] drm/amdgpu/gfx11: handle priority setup for gfx pipe1 Alex Deucher
2024-05-02 21:42 ` [PATCH 3/3] drm/amdgpu/gfx11: enable gfx pipe1 hardware support Alex Deucher
@ 2024-05-07 13:26 ` Alex Deucher
2024-05-10 23:01 ` Alex Deucher
2 siblings, 1 reply; 6+ messages in thread
From: Alex Deucher @ 2024-05-07 13:26 UTC (permalink / raw)
To: Alex Deucher; +Cc: amd-gfx
Ping on this series?
On Thu, May 2, 2024 at 6:02 PM Alex Deucher <alexander.deucher@amd.com> wrote:
>
> Use correct ref/mask for differnent gfx ring pipe. Ported from
> ZhenGuo's patch for gfx10.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index ad6431013c738..81a35d0f0a58e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -5293,7 +5293,7 @@ static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> }
> reg_mem_engine = 0;
> } else {
> - ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
> + ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
> reg_mem_engine = 1; /* pfp */
> }
>
> --
> 2.44.0
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] drm/amdgpu/gfx11: select HDP ref/mask according to gfx ring pipe
2024-05-07 13:26 ` [PATCH 1/3] drm/amdgpu/gfx11: select HDP ref/mask according to gfx ring pipe Alex Deucher
@ 2024-05-10 23:01 ` Alex Deucher
0 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2024-05-10 23:01 UTC (permalink / raw)
To: Alex Deucher; +Cc: amd-gfx
Ping again. This series enables a high priority gfx queue on gfx11,
similar to gfx10.
Alex
On Tue, May 7, 2024 at 9:26 AM Alex Deucher <alexdeucher@gmail.com> wrote:
>
> Ping on this series?
>
> On Thu, May 2, 2024 at 6:02 PM Alex Deucher <alexander.deucher@amd.com> wrote:
> >
> > Use correct ref/mask for differnent gfx ring pipe. Ported from
> > ZhenGuo's patch for gfx10.
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> > index ad6431013c738..81a35d0f0a58e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> > @@ -5293,7 +5293,7 @@ static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> > }
> > reg_mem_engine = 0;
> > } else {
> > - ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
> > + ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
> > reg_mem_engine = 1; /* pfp */
> > }
> >
> > --
> > 2.44.0
> >
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3] drm/amdgpu/gfx11: select HDP ref/mask according to gfx ring pipe
@ 2024-05-13 20:25 Alex Deucher
0 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2024-05-13 20:25 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use correct ref/mask for differnent gfx ring pipe. Ported from
ZhenGuo's patch for gfx10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index c87943f6c4436..c8c055ef2f3c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -5294,7 +5294,7 @@ static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
}
reg_mem_engine = 0;
} else {
- ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
+ ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
reg_mem_engine = 1; /* pfp */
}
--
2.45.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-05-13 20:25 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2024-05-02 21:42 ` [PATCH 3/3] drm/amdgpu/gfx11: enable gfx pipe1 hardware support Alex Deucher
2024-05-07 13:26 ` [PATCH 1/3] drm/amdgpu/gfx11: select HDP ref/mask according to gfx ring pipe Alex Deucher
2024-05-10 23:01 ` Alex Deucher
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